The Chip Design and Verification Stage Stays a Bottleneck for R&D Effectivity
There has lengthy been an effectivity bottleneck within the chip design and verification stage. FPGA and digital IC entrance – finish R&D often contain understanding necessities, disassembling the structure, writing RTL, constructing take a look at platforms, conducting simulation verification, analyzing waveforms, finding issues, and making a number of rounds of modifications. The above processes extremely rely on the expertise of senior engineers, leading to lengthy R&D cycles and excessive collaboration prices. Particularly, the verification and debugging phases usually eat a considerable amount of time. The marketing strategy reveals that SoC verification might eat greater than 70% of the event cycle, and it takes a median of 16 to twenty hours to find a single bug. For chip design firms, FPGA R&D enterprises, scientific analysis establishments, and college laboratories, how one can shorten the cycle from necessities to verifiable engineering outcomes is changing into a key challenge affecting R&D effectivity and undertaking supply certainty.
IC Coder, launched by Chengdu Pengye Jiantu Expertise, is an AI clever agent platform constructed round this ache level. Completely different from common – goal code assistants, IC Coder will not be solely aimed on the single job of “writing code”, however on the complete strategy of chip design and verification, overlaying necessities evaluation, Spec era, RTL writing, automated TestBench era, simulation verification, waveform evaluation, EDA interplay, and drawback restore. The undertaking staff positions it as knowledgeable – stage AI R&D platform for FPGA improvement, digital IC entrance – finish design, chip perform verification, IP core improvement, and SoC subsystem prototype verification, hoping to let AI enter the primary strategy of actual – world engineering from an auxiliary Q&A software.
From Code Era to Engineering Closed – Loop
The core capabilities of IC Coder come from its self – developed chip design particular mannequin and Multi – Agent multi – clever agent system. The platform first disassembles the pure – language necessities enter by customers to type a structured Spec, after which additional generates RTL code, TestBench, simulation duties, and waveform evaluation outcomes. In contrast with common – goal AI that generates a bit of code after which leaves it to engineers to evaluate, IC Coder emphasizes the closed – loop skill of “era – verification – iteration”, that’s, by the suggestions of compilers, simulators, waveform evaluation instruments, and EDA instruments, it constantly discovers issues and promotes code restore.
On the engineering toolchain stage, IC Coder helps docking with mainstream EDA instruments resembling Vivado and TD, and might learn suggestions info resembling synthesis, structure and routing, timing evaluation, and operation logs by scripts. The waveform evaluation skill is used to parse VCD recordsdata, observe sign modifications, and find potential logical issues, in order that the AI output is not restricted to textual content outcomes however mixed with engineering proof. For enterprise clients, the platform additionally offers non-public deployment, intranet operation, native mannequin supply, and permission administration to satisfy the necessities of chip R&D for code safety, knowledge isolation, and course of management.
A typical case disclosed by the undertaking staff exhibits that within the industrial digital camera picture acquisition and DDR cache management subsystem undertaking, the normal mannequin requires a staff of about 5 folks and 60 working days to finish the related improvement and verification; after utilizing IC Coder, the undertaking was compressed to a staff of about 2 folks and three working days to finish the phased duties. This knowledge comes from the undertaking staff’s inner circumstances, and extra tasks nonetheless have to be constantly verified in situations of various complexities, however it displays the effectivity – enchancment potential of AI closed – loop instruments in repetitive coding, take a look at platform era, simulation suggestions, and drawback location.
Commercialization Verification and Financing Plan
By way of market positioning, IC Coder targets the cross – market of “industrial software program, chip R&D, and AI Agent”. The trade knowledge cited within the marketing strategy exhibits that the worldwide Digital System Design trade was value about $19.25 billion in 2024, and there are greater than 3,600 chip design firms in China. The undertaking staff believes that chip design firms, FPGA and digital {hardware} R&D enterprises, scientific analysis establishments, college laboratories, and modern R&D groups are the core buyer teams that IC Coder focuses on serving within the early stage. In response to its calculations, the variety of home core institutional clients that may be served is anticipated to exceed 1,000 within the subsequent 3 to five years. The mixed income from platform authorization, non-public deployment, operation and upkeep implementation, prolonged seats, skilled design companies, and AI personalized R&D will represent the primary business area.
By way of enterprise mannequin, IC Coder adopts a parallel strategy of platform authorization, non-public deployment, cloud service subscription, trade options, {and professional} design companies. Enterprise clients pay extra consideration to knowledge safety, course of adaptation, and R&D effectivity enchancment. Due to this fact, non-public deployment, native mannequin supply, and enterprise – stage supply companies would be the focus of early – stage income; for universities and particular person builders, the consumer protection shall be expanded by the Net terminal, plug – in terminal, course cooperation, and light-weight subscription to precipitate actual necessities and engineering knowledge. In the long term, the undertaking staff additionally plans to increase from the FPGA R&D platform to instructions resembling digital IC entrance – finish, SoC subsystems, edge – aspect clever chips, NPU modules, and IP authorization.
In response to the undertaking staff, about three months after the discharge of IC Coder, it has reached greater than 10 main semiconductor enterprise clients, greater than 50 mid – tier clients, lined greater than 30 universities, with a MAU of greater than 5,000, and a cumulative saving of greater than 100,000 hours of improvement time. The undertaking has develop into an official ecological associate of ANlogic’s “College Program” and has made phased progress in college laboratory co – development, offline coaching, enterprise buyer attain, and procurement conversion. By way of the staff, the founder, Cai Jietao, has lengthy been deeply concerned within the FPGA and digital IC fields, and the core staff covers capabilities in chip R&D, AI productization, platform engineering, non-public supply, and college ecological cooperation.
By way of financing, the undertaking staff has self – invested 5 million yuan and at present plans to launch an angel – spherical financing of 8 million yuan. The funds shall be primarily used for strengthening the particular mannequin for chip design and verification, enhancing the IDE/plug – in/Net – finish merchandise, changing B – finish non-public – deployment clients, rising C – finish customers, and constructing an trade information base. For traders, the core attraction of IC Coder is that the pattern of AI Coding has been verified within the software program improvement area, whereas the chip R&D, as knowledgeable state of affairs with greater thresholds, excessive buyer unit costs, and powerful safety necessities, nonetheless lacks a mature platform – kind product. IC Coder tries to mix vertical fashions, clever agent workflows, EDA toolchain collaboration, and enterprise – stage supply capabilities throughout this window interval to develop into an early participant within the AI – pushed chip R&D infrastructure.