For many years, the computing business has adopted a easy system: make transistors smaller and pack extra of them onto a chip. That technique fueled the extraordinary rise in computing energy predicted by Moore’s legislation. However as parts strategy atomic scales, engineers are more and more operating into the bodily limits of silicon and the results of quantum mechanics.
Many researchers imagine the following main advance will come not from shrinking units additional, however from constructing upward.
A group led by College of Illinois Grainger Faculty of Engineering supplies science and engineering professor Qing Cao has demonstrated a brand new technique for stacking a number of layers of silicon electronics instantly on high of each other. The strategy may dramatically improve computing density, enhance efficiency, and cut back vitality consumption whereas extending the progress that has pushed the semiconductor business for greater than half a century.
“Take one thing so simple as static random-access reminiscence, which is common in CPUs and GPUs. In the present day it takes six microelectronic units referred to as transistors on a single airplane to retailer one bit of knowledge. With vertical integration, you possibly can distribute them throughout a number of layers. It is like changing a sprawling suburb with high-rises: you get the identical performance, however the spatial footprint is decreased whereas making communication between layers quicker and extra environment friendly,” Cao defined.
The researchers report that their course of achieves gadget yields of 98‒100% whereas utilizing commonplace single-crystalline silicon, the semiconductor materials that underpins fashionable electronics. The outcomes recommend the approach may finally be adopted by business chip producers.
“Vertical integration is already beginning to make its method into business units, significantly in specialised AI {hardware}, however monolithic integration is what unlocks the complete promise of 3D chips,” Cao stated. “For the primary time, we’ve got met the thermal price range of monolithic 3D integration utilizing commonplace single-crystalline silicon and delivered unprecedented efficiency.”
The findings have been printed in Nature, a journal that not often options silicon microelectronics analysis articles.
Why the Semiconductor Business Is Trying Upward
For roughly 60 years, Moore’s legislation has guided chip growth. The precept predicts that transistor density on built-in circuits will double about each two years, resulting in quicker and extra environment friendly processors.
That development has held remarkably nicely, however it’s changing into more and more tough to maintain.
“In a way, we’re hitting a restrict imposed by physics,” Cao stated. “When you take a look at the precise dimension of transistors, they don’t seem to be getting smaller, particularly by way of their contacted gate pitch. It’s because we’re changing into restricted by the intrinsic materials properties of silicon and the elemental guidelines of quantum mechanics. If we will sustain the development of accelerating processing energy of our microprocessors, we’ve got to begin pondering past simply squeezing extra units on a single floor.”
Stacking units vertically provides a horny different. As a substitute of constant to shrink particular person transistors, engineers can place a number of layers of circuits on high of each other. This not solely creates extra room for parts but in addition shortens wiring distances, decreasing parasitic capacitance and considerably rising communication bandwidth between completely different components of a chip.
These benefits are significantly vital for synthetic intelligence and different data-intensive computing functions.
The Promise of Monolithic 3D Chips
Present business 3D chip applied sciences already use stacking, however they sometimes contain manufacturing semiconductor units on separate wafers earlier than bonding them collectively. Examples embody high-bandwidth reminiscence and AMD’s 3D V-Cache know-how.
Whereas profitable, these strategies have limitations. Alignment between layers is comparatively coarse, and the vertical connections generally known as through-silicon vias (TSVs) are comparatively massive and sparse.
Monolithic three-dimensional integration takes a unique strategy. Quite than becoming a member of accomplished wafers, every new gadget layer is fabricated instantly on high of the earlier one. This enables a lot denser vertical connections, smaller distances between layers, and alignment accuracy measured in nanometers.
Researchers have pursued this idea for years as a result of it may improve interlayer connectivity by an element of 10 to 100 in contrast with typical stacking strategies.
Fixing the Warmth Drawback
The most important impediment to monolithic integration has been temperature.
Producing high-quality crystalline silicon and fabricating high-performance semiconductor units sometimes requires temperatures approaching 1,000 levels Celsius. Nevertheless, as soon as metallic interconnects are already current in a accomplished circuit layer, such temperatures would destroy them.
“Usually, the business accepts that after the primary layer of circuits is full, the thermal price range restrict for any further layers is 400 levels Celsius,” Cao stated. “Researchers in each academia and business have tried to get round this by working with semiconductor supplies apart from single-crystalline silicon for the higher layers. However the ensuing units all inevitably undergo from points with efficiency and reliability.”
Earlier efforts have explored options together with polycrystalline silicon, amorphous and nanocrystalline metallic oxides, carbon nanotubes, and two-dimensional semiconductors. Nevertheless, these supplies usually introduce efficiency limitations or defects that create a mismatch with the silicon transistors within the backside layer.
Ultrathin Silicon Nanomembranes Allow Low Temperature Manufacturing
The Illinois group developed a course of that preserves some great benefits of single-crystal silicon whereas staying nicely under the thermal restrict.
The strategy begins by creating ultrathin freestanding silicon nanomembranes from a donor wafer. These membranes are then transferred onto a receiving substrate that already accommodates accomplished circuitry utilizing a roll laminator. The bonding course of requires temperatures of not more than 200 levels Celsius.
As a result of the silicon layers retain their crystalline high quality, the ensuing units preserve robust efficiency and reliability whereas remaining safely inside the thermal price range required for monolithic integration.
“Our technique will not be solely simpler to implement with decrease value, however it has a number of benefits over earlier approaches to stack silicon wafers,” Cao stated. “The membranes we transferred are solely 10 nanometers thick or much less, in comparison with the five hundred to 700 micrometers thickness of a typical wafer. As a result of they’re skinny, these membranes are mechanically versatile to evolve to the underlying floor. This conformality helps keep away from interfacial defects like voids, that are widespread when making an attempt to pressure two inflexible wafers collectively by way of wafer bonding.”
Excessive Efficiency With Three Stacked Layers
The researchers additionally redesigned the transistor structure.
Conventional transistor manufacturing depends on a course of referred to as doping, which introduces impurities into silicon to regulate electrical habits. That course of often requires temperatures above 600 levels Celsius.
To keep away from these temperatures, the group used junctionless transistors. In these units, the silicon is uniformly and closely doped earlier than the stacking course of begins. The extraordinarily skinny silicon movies nonetheless enable efficient management by the transistor gate, whereas the excessive doping ranges assist cut back parasitic contact resistance.
Utilizing this technique, the researchers fabricated three stacked layers containing 625 transistors every. The units confirmed robust uniformity and excessive manufacturing yield.
Their output present densities matched these of typical silicon transistors fabricated on bulk wafers at a lot increased temperatures. Additionally they outperformed monolithic units comprised of different supplies by no less than an element of three to 4.
The group related the layers utilizing vertical metallic interconnects and efficiently demonstrated three-dimensional logic circuits in addition to static random-access reminiscence cells.
Towards Industrial Semiconductor Manufacturing
Based on Cao, probably the most important consequence could be the scalability of the method.
“However most significantly, we have proven that this course of is scalable,” Cao stated. “You may preserve stacking layers past the three we demonstrated. And the method will yield high-performing transistors with excessive yield and low variability. We now have a powerful basis for transferring this know-how and demonstrating its instant promise in an industrial semiconductor foundry.”
The work was carried out via Illinois Grainger Engineering’s Heart for Superior Semiconductor Chips with Accelerated Efficiency, whose business companions embody IBM, Intel, and the Taiwan Semiconductor Manufacturing Firm.
The researchers are actually making ready to switch the know-how to an industrial semiconductor foundry, an vital step towards bringing true monolithic 3D silicon chips into business manufacturing.
Further contributors to the examine included Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian-Min Zhuo.
Funding was offered by the Nationwide Science Basis, business companions of Illinois Grainger Engineering’s Heart for Superior Semiconductor Chips with Accelerated Efficiency, and the Silicon Crossroads Microelectronics Commons Hub.